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| C5002 low skew multiple frequency pci clock generator with emi reducing sscg approved product cypress semiconductor corporation 525 los coches st. document#: 38-07014 rev. ** 5/4/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 1 of 16 http://www.cypress.com product features produces pci output clocks that are individually selectable for 33.3 or 66.6 mhz under smbus or strapping control. separate output buffer power supply for reduced noise, crosstalk and jitter. input clock frequency standard 14.31818 mhz output clocks frequency individually selectable via smbus or hardware bi-directional pin strapping. sscg emi reduction at 1.0% width individual clock disables via smbus control all output clocks skewed within a 500 ps window cycle to cycle jitter 250 ps output duty cycle is automatically 50% ( 10%) adjusted clock feed through mode and oe pins for logic testing glitchless clock enabling and disabling transitions 28-pin tssop or ssop package block diagram output enable logic functionality table oe clk(0:9) pll 1 (high) enabled running 0 (low) tri state stopped* *see output enable control section of this datasheet. pin configuration vdd1 ref-clk0/s0 clk1/s1 vss vdd2 clk2/s2 clk3/s3 vss vdd3 clk4/s4 clk5/s5 vss vdd4 clk6/s6 vdd xin xout vss oe sclk sdata vss vss clk9/s9 clk8/s8 vdd5 vss clk7/s7 28 27 26 25 24 23 22 21 20 19 18 17 16. 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 xin sclk sdata xout clk4/s4 clk1/s ref- clk0/s0 clk2/s 2 clk3/s3 clk7/s7 clk8/s8 clk9/s9 clk5/s5 clk6/s6 smbus logic 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 4, 8 pll oe m u x reference oscillator
C5002 low skew multiple frequency pci clock generator with emi reducing sscg approved product cypress semiconductor corporation 525 los coches st. document#: 38-07014 rev. ** 5/4/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 2 of 16 http://www.cypress.com pin description pin number pin name pwr i/o description 2 xin vdda i this pin is the connection point for the devices loop reference frequency. this may be either a cmos 3.3 volt reference clock or the output of an external crystal. a nominal 14.31818 mhz frequency must be supplied to obtain the frequencies listed on this data sheet 3 xout vdda o this pin the devices output drive that is to be used when an external crystal is used. in this configuration the device provides the analog gain function of a crystal oscillator. when the device is being supplied with an external reference frequency, this pin is left disconnected. 1 vdda - pwr this pin is the power supply source for the internal pll circuitry and core control logic. it should be bypassed separately from all other device vdd supply pins. 5 oe - i output enable. see logic table on page 1 for functionality 12, 16, 20, 24, 28 vdd - pwr logic power for all buffers 6 sdata vdda i/o smbus serial data pin 7 sclk vdda o smbus serial interface clock pin 27 ref- clk0/s0 vdd1 o 26 clk1/s1 vdd1 o 23 clk2/s2 vdd2 o 22 clk3/s3 vdd2 o 19 clk4/s4 vdd3 o 18 clk5/s5 vdd3 o 15 clk6/s6 vdd4 o 14 clk7/s7 vdd4 o 11 clk8/s8 vdd5 o 10 clk9/s9 vdd5 o individual output clocks and power up divisor select pins. each of these pins is both a clock output pin and, at power up, a temporary input pin. when they act as an input pin they set the initial output frequency of the device to either the input frequency or half of the input frequency. subsequently, the divisor may be changed or disabled via the device?s smbus register bits. reference clock and its programmable input value is saved internally for when it pci clock function is selected. 4, 8, 9, 13, 17, 21, 25 vss - pwr ground pins for the chip. 1 vdd - pwr power for core logic 28 vdd1 - pwr power for clk1 and clk2 output buffers 24 vdd2 - pwr power for clk3 and clk4 output buffers 20 vdd3 - pwr power for clk5 and clk6 output buffers 16 vdd4 - pwr power for clk7 and clk8 output buffers 12 vdd5 - pwr power for clk9 and clk10 output buffers a bypass capacitor (0.1 mf) should be placed as close as possible to each vdd pin. C5002 low skew multiple frequency pci clock generator with emi reducing sscg approved product cypress semiconductor corporation 525 los coches st. document#: 38-07014 rev. ** 5/4/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 3 of 16 http://www.cypress.com spectrum spread clocking spectrum analysis spectrum spreading selection table unspread frequency in mhz down spreading desired (actual) f min (mhz) f center (mhz) f max (mhz) spread (%) 33.3 (xx.x) 33.00 33.16 33.3 +0 -1.00% 66.6 (xx.x) 66.00 66.33 66.6 +0 -1.00% frequency (mhz) amplitude (db) without spectrum spread with spectrum spread down spread C5002 low skew multiple frequency pci clock generator with emi reducing sscg approved product cypress semiconductor corporation 525 los coches st. document#: 38-07014 rev. ** 5/4/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 4 of 16 http://www.cypress.com power up bi-directional pin timing (all clock outputs) note: a pull-up or logic high programming voltage will select a 66.6 mhz output clock frequency on that specific pin. a logic low level will select a 33.3 mhz clock frequency in that specific pin. output frequency selections the device contains 3 specific output mode type pins. they are: ref-clk0/s0 this pin powers up as a 33.3 or 66.6 mhz pci clock. via smbus command byte 1 bit 4 it may be changed to be a 14.318 mhz clock. when it is acting as a pci clock its frequency may be changed between 33 and 66 mhz using smbus command byte 1 bit 3. the pci clock may also be initially set at device power up using the bi-directional programming capability of the pin (device pin number 27) clk (1:8) these are dual frequency pci clock pins that may be stopped enabled and have their frequency changed at power up and then on the fly (at any time) via their respective smbus register control bits. clk9/s9 this bit acts in the same manner as the clk (1:8) bits. additionally by selection in smbus byte 3 bits 5 and 6 it can output both 16.5 mhz or 8.25 mhz on its pin. like the other clock pins smbus byte 3 bit 6 is initially set (via the clocks bi- directional; pin function) at power up depending on the level of the clocks pin. note: clocks ref-clk0/s0 (pin 27) and clk1/s1 (pin 26) are powered from vdd1 (pin 28). this data sheet characterizes the guaranteed performance of these 2 clocks with respect to jitter and skew. designers that use this device need to understand that if these 2 clocks are operated at different frequencies (e.g., pin 27 is set to the ref output mode while pin 26 is enabled at either 33 pr 66 mhz frequency mode) that the data sheet values of these clocks will not be guaranteed. it is therefor prudent to disable the clk1 output when the ref-clk0/s0 output has been programmed to output a 14.31818 mhz clock to realize the devices best performance. power supply vdd clk (0:9) hi-z ( tristate ) , in p uts toggle, outputs fig.1 C5002 low skew multiple frequency pci clock generator with emi reducing sscg approved product cypress semiconductor corporation 525 los coches st. document#: 38-07014 rev. ** 5/4/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 5 of 16 http://www.cypress.com output enable control the output enable pin (pin 5) on this device serves two (2) purposes. the primary function is to force all clock outputs to a tri-state electrical mode. this is done to support automated testing of fabricated pcb assemblies. the second function of this pin is to bring the internal circuitry of the device to a lower power mode when the pin is driven to a logic low level. in this mode, all unneeded circuitry (e.g., the pll, counters and clock control logic) have their power removed. designers who use this functionality should pay close attention to the t oel characteristic listed in the ac parameters section of this datasheet. this function is particularly useful in mobil designs where power savings is a crucial design factor. data stored in the smbus registers is maintained during oe active periods. application note for selection on bi-directional pins pins 10, 11, 14, 15, 18, 19, 22, 23, 26 and 27 are power up bi-directional pins and are used for selecting power up output frequencies of this devices output clocks (see pin description, page 2). during power-up of the device, these pins are in input mode, therefore, they are considered input select pins internal to the ic, these pins have a large value pull-up each (250k ?) , therefore, a selection ?1? is the default and will select a 66 mhz output frequency. if the system uses a slow power supply (over 5 ms settling time), then it is recommended to use an external pull-up (rup) in order to insure a high selection. in this case, the designer may choose one of two configurations, see fig. 3a and fig. 3b. fig. 3a represents an additional pull up resistor 50k ? connected from the pin to the power line, which allows a faster pull to a high level. if a selection ?0? is desired, then a jumper is placed on jp1 to a 5k ? resistor as implemented as shown in fig. 3a. please note the selection resistors (rup and rdn ) are placed before the damping resistor (rd) close to the pin. fig. 3b represents a single resistor 10k ? connected to a 3-way jumper, jp2. when a ?1? selection is desired, a jumper is placed between leads 1 and 3. when a ?0? selection is desired, a jumper is placed between leads 1 and 2. if the system power supply is fast (less than 5 msec settling time), then fig 3a only applies and pull up rup resistor is not necessary. the electrical length of the trace that connects the selection resistor to the devices pin should be kept as short as possible. load load fig. 3a fig. 3b vdd vdd rup 50k rd C5002 bidirectional jp1 jumper jp2 3 way jumper rsel 10k rd C5002 bidirectional rdn 5k C5002 low skew multiple frequency pci clock generator with emi reducing sscg approved product cypress semiconductor corporation 525 los coches st. document#: 38-07014 rev. ** 5/4/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 6 of 16 http://www.cypress.com input and output relationships the device acts a pci clock generator. output clocks may be individually controlled to be either 33.3 or 66.6 mhz in frequency by setting or clearing the clocks respective smbus control register bit. all output clocks are rising edge aligned to within a shared 500 ps window. there is no specified relationship between the input reference clock and the output clocks. clock enable functions and timing each output clock may be either disabled or enabled by either setting or clearing its respective smbus register control bit. all clocks are stopped in the low state. all clocks maintain a valid high period before transitioning from running to stopped. the clocks transition between running and stopped occurs immediately after the smbus register bit is cleared and the clock transitions to a low state. see figure below. internal clock i 2 c register bit 2 output 1 output a: represents one output 2 clock cycle (one 33.3 mhz cycle period). b: represents one output clock 1 cycle (one 66.6 mhz cycle period). output frequency change relationships the smbus registers are initially set (initialized) by the voltage levels present on the clocks output pins at power up. subsequently these bits may be changed via smbus commands. output clocks have the capability to be changed, on the fly, via the devices smbus register bits. if synchronous switching is required, it may be achieved by first disabling a specific clock, changing its frequency and then re-enabling it via the smbus register control bits that are provided for these functions. synchronous switching is defines at the changing of the output frequency of a clock from one frequency to another in such a manner as to not produce any clock cycles shorter than the higher of the 2 frequencies or longer than the period of the lower of the 2 frequencies. the disable and enable smbus register bit control of each clock is logically implemented to eliminate clock glitches when each clock is either enabled or enabled. b a C5002 low skew multiple frequency pci clock generator with emi reducing sscg approved product cypress semiconductor corporation 525 los coches st. document#: 38-07014 rev. ** 5/04/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 7 of 16 http://www.cypress.com caution: switching clock frequencies without first disabling the clock may produce an output clock glitch (short or stretched period clock) during frequency transition !) 2-wire smbus control interface the 2-wire control interface implements write block mode write only slave interface. sub addressing is not supported, thus all preceding bytes must be sent in order to read or change one of the control bytes. the 2-wire control interface allows each clock output to be individually controlled. during normal data transfer, the sdata signal only changes when the sdclk signal is low, and is stable when sdclk is high. there are two exceptions to this. a high to low transition on sdata while sdclk is high is used to indicate the start of a data transfer cycle. a low to high transition on sdata while sdclk is high indicates the end of a data transfer cycle. data is always sent as complete 8-bit bytes, after which an acknowledge is generated. the first byte of a transfer cycle is a 7-bit address with a read/write bit as the lsb (bit 0). data is transferred msb (bit 7) first. the device will respond to writes up to 6 bytes (max) of data to address d0. the device will not respond to any other control interface conditions. serial control registers note: the pin# column lists the affected pin number where applicable. the @pup column gives the state at true power up. bytes are set to the values shown only on true power up. following the acknowledge of the address byte (d0), two additional bytes must be sent: 1) ? command code ? byte, and 2) ? byte count ? byte. although the data (bits) in these two bytes are considered ?don?t care?; they must be sent and will be acknowledged. after the command code and the count bytes have been acknowledged, the described sequence below (byte 0, byte 1, byte2,) will be valid and acknowledged. byte 0: function select register (1 = enable, 0 = stopped) bit @pup pin# description 7 1 14 clk7 (active = 1, forced low = 0) 6 1 15 clk6 (active = 1, forced low = 0) 5 1 18 clk5 (active = 1, forced low = 0) 4 1 19 clk4 (active = 1, forced low = 0) 3 1 22 clk3 (active = 1, forced low = 0) 2 1 23 clk2 (active = 1, forced low = 0) 1 1 26 clk1 (active = 1, forced low = 0) 0 1 27 clk0 (active = 1, forced low = 0) C5002 low skew multiple frequency pci clock generator with emi reducing sscg approved product cypress semiconductor corporation 525 los coches st. document#: 38-07014 rev. ** 5/04/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 8 of 16 http://www.cypress.com serial control registers (cont.) byte 1: clock register (1 = enable, 0 = stopped) bit @pup pin# description 7 1 - 0= test mode ( xin replaces vco output ), 1=normal 6 0 10 bit 6 bit 5 pci9 frequency ----------------------------------------- 5 hw 10 0 0 33 mhz 0 1 66 mhz 1 0 16.5 mhz 1 1 8.25 mhz 4 0 27 ref-clk0 mode ( 1 = ref, 0 = pci0 ) 3 hw 27 clk0 (33.3 mhz = 0, 66.6 mhz = 1)(if byte 3 bit 4=0) 2 0 - sscg (off = 0, on = 1) 1 1 10 clk9 ( active = 1, forced low = 0 ) 0 1 11 clk8 ( active = 1, forced low = 0 ) byte 2: clock register (1 = 66.6 mhz, 0 = 33.3 mhz) bit @pup pin# description 7 hw 11 clk8 (33.3 mhz = 0, 66.6 mhz = 1) 6 hw 14 clk7 (33.3 mhz = 0, 66.6 mhz = 1) 5 hw 15 clk6 (33.3 mhz = 0, 66.6 mhz = 1) 4 hw 18 clk5 (33.3 mhz = 0, 66.6 mhz = 1) 3 hw 19 clk4 (33.3 mhz = 0, 66.6 mhz = 1) 2 hw 22 clk3 (33.3 mhz = 0, 66.6 mhz = 1) 1 hw 23 clk2 (33.3 mhz = 0, 66.6 mhz = 1) 0 hw 26 clk1 (33.3 mhz = 0, 66.6 mhz = 1) note : hw = power up programmed via hardware (voltage at pin). C5002 low skew multiple frequency pci clock generator with emi reducing sscg approved product cypress semiconductor corporation 525 los coches st. document#: 38-07014 rev. ** 5/04/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 9 of 16 http://www.cypress.com maximum ratings voltage relative to vss: -0.3v voltage relative to vdd: 0.3v storage temperature: 0oc to + 125oc operating temperature: 0oc to +70oc maximum power supply: 7v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: vss<(vin or vout) C5002 low skew multiple frequency pci clock generator with emi reducing sscg approved product cypress semiconductor corporation 525 los coches st. document#: 38-07014 rev. ** 5/04/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 11 of 16 http://www.cypress.com crystal and reference oscillator parameters characteristic symbol min typ max units conditions frequency f o 12.00 14.31818 16.00 mhz tolerance tc - - +/-100 ppm calibration note 1 ts - - +/- 100 ppm stability (ta -10 to +60c) note 1 ta - - 5 ppm aging (first year @ 25c) note 1 mode om - - - parallel resonant pin capacitance cp 32 pf capacitance of xin and xout pins to ground (each) dc bias voltage v bias 0.3vdd vdd/2 0.7vdd v startup time ts - - 30 s load capacitance cl - 16 - pf see calculation section below effective series resistance (esr) r1 - - 40 ohms power dissipation dl - - 0.10 mw note 1 shunt capacitance co - -- 8 pf crystal?s internal package capacitance (total) for maximum accuracy, the total circuit loading capacitance should be equal to cl. this loading capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (cp) in parallel with any circuit traces, the clock generator and any onboard discrete load capacitors. budgeting calculations typical trace capacitance, (< half inch) is 4 pf, load to the crystal is therefore = 2.0 pf clock generator internal pin capacitance of 32 pf, load to the crystal is therefore = 16.0 pf the total capacitance see by the crystal would therefore be = 18.0 pf. note 1: it is recommended but not mandatory that a crystal meets these specifications. C5002 low skew multiple frequency pci clock generator with emi reducing sscg approved product cypress semiconductor corporation 525 los coches st. document#: 38-07014 rev. ** 5/04/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 12 of 16 http://www.cypress.com package drawing and dimensions 28 pin ssop outline dimensions inches millimeters symbol min nom max min nom max a 0.068 0.073 0.078 1.73 1.86 1.99 a 1 0.002 0.005 0.008 0.05 0.13 0.21 a2 0.066 0.068 0.070 1.68 1.73 1.78 b 0.010 0.012 0.015 0.25 0.30 0.38 c 0.005 0.006 0.009 0.13 0.15 0.22 d 0.397 0.402 0.407 10.07 10.20 10.33 e 0.205 0.209 0.212 5.20 5.30 5.38 e 0.0256 bsc 0.65 bsc h 0.301` 0.307 0.311 7.65 7.80 7.90 a 0 4 8 0 4 8 l 0.022 0.030 0.037 0.55 0.75 0.95 b e e h a l c d a a 1 a 2 C5002 low skew multiple frequency pci clock generator with emi reducing sscg approved product cypress semiconductor corporation 525 los coches st. document#: 38-07014 rev. ** 5/04/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 13 of 16 http://www.cypress.com package drawing and dimensions (cont.) bo surfaces roughness: 6+ 27n(rz) d -b- 385 e1 l20 r0.1 b e -c- c 0.07 rd 4 [10 typ r1.30 1.0 0.10~0.15 0.00 ~ 0.05 section v-v 0.05 max. 0.05 max. 1.0 1.0 e r0.15 a a 1 0.25 a2 r l1 l a 8 b c c1 b1 detail b .08 cb a detail a 14 typ 28 pin tssop dimensions inches millimeters symbol min nom max min nom max a - - 0.047 - - 1.20 a1 0.002 0.004 0.006 0.05 0.10 0.15 a2 0.037 0.039 0.041 0.95 1.00 1.05 l 0.019 0.023 0.029 0.50 0.60 0.75 l1 0.035 0.039 0.043 0.90 1.00 1.10 b 0.007 - 0.011 0.19 - 0.30 b1 0.007 0.008 0.010 0.19 0.22 0.25 c 0.004 - 0.007 0.105 - 0.175 c1 0.004 0.005 0.006 0.105 0.125 0.145 0 - 8 0 - 8 e 0.026 bsc 0.65 bsc d 0.378 0.382 0.386 9.6 9.7 9.8 e 0.244 0.252 0.260 6.2 6.4 6.6 e1 0.169 0.173 0.177 4.3 4.4 4.5 r 0.035 - - 0.9 - - C5002 low skew multiple frequency pci clock generator with emi reducing sscg approved product cypress semiconductor corporation 525 los coches st. document#: 38-07014 rev. ** 5/04/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 14 of 16 http://www.cypress.com ordering information part number package type production flow C5002btb 28 pin tssop commercial, 0oc to +70oc C5002byb 28 pin ssop commercial, 0oc to +70oc note: the ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. marking: example: cypress C5002byb date code, lot # C5002 b y b flow b = commercial, 0oc to + 70oc package y = ssop t = tssop revision device number C5002 low skew multiple frequency pci clock generator with emi reducing sscg approved product cypress semiconductor corporation 525 los coches st. document#: 38-07014 rev. ** 5/04/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 15 of 16 http://www.cypress.com disclaimer cypress semiconductor corporation reserves the right to change or modify the information contained in this datasheet and the products described therein, without prior notice. cypress semiconductor corporation does not convey any license under its patent rights nor the rights of others. charts, drawings and schedules contained in this datasheet are provided for illustration purposes only and they vary depending upon specific applications. cypress semiconductor corporation makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does cypress semiconductor corporation assume any liability arising out of the application or use of any product or circuit described herein. cypress semiconductor corporation does not authorize use of its products as critical components in any application in which the failure of the cypress semiconductor corporation product may be expected to result in significant injury or death, including life support systems and critical medical instruments. C5002 low skew multiple frequency pci clock generator with emi reducing sscg approved product cypress semiconductor corporation 525 los coches st. document#: 38-07014 rev. ** 5/04/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 16 of 16 http://www.cypress.com document title: C5002 low skew miltiple frequency pci clock generator with emi reducing sscg document number: 38-07014 rev. ecn no. issue date orig. of change description of change ** 109129 08/29/01 ndp convert from imi to cypress |
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